The present invention relates, in general, to flash memory devices and, more particularly, to a flash memory device and a method of erasing the same, in which backward tunneling charges can be reduced at the time of an erase operation.
In a method of storing data by using a polysilicon layer, used in a flash memory device, as a floating gate, a line width is miniaturized as memory becomes high integrated, and capacitance occurs. Accordingly, there are problems in which the speed and stability of products are lowered.
In recent years, to overcome the shortcomings of the flash memory device, active research has been done on Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory.
The SONOS flash memory generally has a structure in which an oxide layer, a nitride layer, an oxide layer and a polycrystalline silicon layer are sequentially stacked over a semiconductor substrate. The nitride layer has an ONO structure in which it is sandwiched between the oxide layers. In the ONO structure, the nitride layer is used as an electric charge-trapping medium. The electric charge trapping medium is a place for storing information of the SONOS flash memory. Thus, the nitride layer is a structure having a similar function as that of a floating gate of typical flash memory.
If an erase operation is performed by using the SONOS flash memory constructed above, an electric field, generated by voltage applied to a control gate, is transferred to a tunnel-insulating layer through a blocking oxide layer.
If the thickness of the blocking oxide layer is more, however, an electric field transferred to the tunnel-insulating layer is weakened at the time of the erase operation, so that the program speed is decreased. Meanwhile, if the thickness of the blocking oxide layer is less, the program speed is increased and backward tunneling charges are also increased and hence the electric charges of the control gate are trapped at the nitride layer through the blocking oxide layer. Due to this, the flash memory device may operate inefficiently.